What is jtag interface

The IEEE These instructions are:. Introduction Advances in silicon design such as increasing device density and, more recently, BGA packaging have reduced the efficacy of traditional testing methods.

Boundary Scan The main advantage offered by utilising boundary scan technology is the ability to set and read the values on pins without direct physical access. Figure 1 — Schematic Diagram of a JTAG enabled device The process of boundary scan can be most easily understood with reference to the schematic diagram shown in figure 1. TCK Test Clock — this signal synchronizes the internal state machine operations. It is sampled at the rising edge of TCK when the internal state machine is in the correct state.

Registers There are two types of registers associated with boundary scan. BSR — this is the main testing data register. It allows other devices in a circuit to be tested with minimal overhead. The file contains details of the Boundary Scan configuration for the device. For more detail on each state, refer to the IEEE This instruction allows the testing of other devices in the JTAG chain without any unnecessary overhead.

However, the device is left in its normal functional mode. During this instruction, the BSR can be accessed by a data scan operation to take a sample of the functional data entering and leaving the device.

Obtaining the IEEE And how can I make use of it? Testing BGA Connections. Disconnecting the control of the pins from the functionality of the enabled device makes boundary scan test development significantly easier than traditional functional test as no device configuration or booting is required to use the pins.

By providing a mechanism to control and monitor all the enabled signals on a device from a four-pin TAP, JTAG significantly reduces the physical access required to test a board. There are two main ways that this boundary scan capability can be used to test a board. The first way, connection testing see next section gives good test coverage, particularly for short circuit faults. Where two JTAG enabled pins are meant to be connected the test will make sure one pin can be controlled by the other.

Where enabled pins are not meant to be connected they are tested for short circuit faults by driving one pin and checking that these values are not read on the other pins. XJTAG will automatically generate the vectors required to run a connection test based on the netlist of a board and JTAG information for the enabled devices. In order to add this open circuit coverage it is necessary to communicate with the peripheral device from boundary scan on the enabled device.

If communication can be verified, there cannot be an open circuit fault. This type of testing can be very simple, for example lighting an LED and asking an operator to verify it has activated, or more complex, for example writing data into the memory array of a RAM and reading it back. The library files contain models for all types of non-JTAG devices from simple resistors and buffers to complex memory devices such as DDR3.

Because boundary scan disconnects the control of the pins on JTAG devices from their functionality the same model can be used irrespective of the JTAG device controlling a peripheral.

Most boards already contain JTAG headers for programming or debug so there are no extra design requirements. In order to run any boundary scan based testing it is necessary to have some information about the implementation of JTAG on the enabled devices on a board. Not at all. One of the key benefits to boundary scan testing is that the only test hardware required is a JTAG controller. Using boundary scan during board bring-up can remove uncertainties — hardware engineers can test prototype boards for manufacturing defects before system testing, and even before firmware is complete.

Test systems developed at this early stage of the product lifecycle can easily be reused, and extended for production. Each BGA device on a board imposes severe restrictions on the testing that can be done using traditional bed-of-nails or flying probe machines. The non-recurring engineering NRE costs of building test fixtures can be prohibitively high.